Emerging Materials for TSV Devices
Three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in three dimensions (3D).
TSV is an important developing technology that utilizes short, vertical electrical connections or “vias” that pass through a silicon wafer to establish an electrical connection from the active side to the backside of the die. TSV provides the shortest interconnect path, creating an avenue for the ultimate in 3D integration.
TSV technology offers greater space efficiencies and higher interconnect densities than wirebonding and flip chip stacking. When combined with micro bump bonding and advanced flip chip technology, TSV technology enables a higher level of functional integration and performance in a smaller form factor.
Semiconductor devices are constantly responding to the demand for “faster, cheaper, smaller”. As consumer electronics become increasingly complex and more compact, devices are expected to deliver more functionality at greater speed in smaller dimensions. In the past, these demands have largely been met through miniaturization of circuits and their components, driven by Moore’s Law and now “More Moore”. However, in recent years 3D integration in the form of wire bond and flip-chip stacking has made its way into mainstream semiconductor manufacturing to address the limitations of physical scaling while delivering greater performance and functionality.
“Through-silicon via” (TSV) is emerging as a method of 3D integration that offers designers more freedom, and greater energy and space efficiencies than wire bonding and flip chip stacking.
TSV is expected to enter the mainstream in 2013-2014, especially for memory devices, embedded logic and heterogeneous applications. 3D integration describes the process of vertically connecting several chips to achieve high functionality-to-volume ratio using established silicon technology and micro fabrication methods.
In TSV, two or more vertically stacked chips are joined by vertical interconnects running through the stack (i.e., across the interface between two or more adjacent chips) and functioning as components of the integrated circuit.
Stacking and connecting (similar or different) die enables the creation of high-performance devices made from components fabricated at non-leading edge geometries.
While two die could be combined using conventional wire bonding techniques, the inductive losses would reduce the speed of data exchange, in turn eroding the performance benefit.
TSV addresses the data exchange issues of wire bonding and offers several other attractive advantages including shorter interconnects between the die, reducing power consumption caused by long horizontal wiring, and eliminating the space and power wasted by buffers (repeaters that propel a signal through a lengthy circuit).
TSV also reduces electrical parasitics in the circuit (i.e., unintended electrical effects), increasing device switching speeds. In addition, TSV accommodates much higher input/output density than wire bonding, which consumes much more space.
TSV Report: Emerging Materials for TSV Devices
Emerging Materials for TSV Devices:
- Reviews anticipated materials needs for potential future devices including interposers, PVD, CMP slurries and pads, plating chemicals, CVD, photoresists, etchants, cleaners and bonding adhesives.
- Discusses the relative challenges of competing TSV technologies
- Targets markets for TSV materials
Table of Contents
1. TSV Background and Business Considerations
- TSV Technology
- Benefit of TSV
- More Moore vs. More than Moore
- Performance Benefits Drive Applications—DRAM
- Performance Benefits Drive Applications— Logic
- Segmentation Approaches
- Key OEMS
- Impact of 450mm
- Leading Consortia
2. TSV Processes and Key Materials
- Silicon Interposer
- Glass Interposer
- Isolation oxide
- PVD—Copper, Barrier and Seed
- Copper Fill
- Copper CMP
- Barrier CMP
- Wafer thinning
- Via Reveal
- Oxide TSV—Depositions and CMP
- Wafer Bonding and Debonding
3. TSV Materials and Forecasts
- Most Likely Scenarios
- TSV Forecasts by Wafer Size by Year, 2011—2016
- TSV as a % of 300mm
- Interposer Forecast
- TSV Total Materials Market ($M), 2011—2016
- Resist, Etch, Clean, Bonding
- CVD, PVD and ECD
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