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Advanced Patterning, 2008—2013BackgroundPhotolithographic patterning is a pivotal process in the manufacture of all ICs, and is vital to delivering the density increases and chip area shrinking in most advanced devices. Today, lithography is facing an uncertain future as EUV once touted for HVM by 2012 has now been delayed to 2016, well into the 16nm node. High index lithography, once a promising technology, has fallen out of favor due to issues of costs, technology readiness, and seemingly insurmountable scientific challenges. The immediate implication of these industry shortcomings is that immersion 193nm lithography involving pitch doubling (double patterning) and ancillary resist materials will continue to play a critical role in sustaining Moore’s Law for the next eight years, down to the 22nm node. Double Patterning
Logic device vendors and research consortia continue to improve and implement immersion lithography in volume manufacturing for 4X nodes. However the path to achieving finer patterns at 3X and 2Xnm nodes remains complex. Interaction between equipment, materials, and processes used in pattern transfer is still a major challenge. Flash vendors have made progress in implementing CVD-based self-aligned double patterning (SADP) based on spacers for 3Xnm, but the path for flash to 2X and 1X nodes remains murky and brings new competitive players and opportunities to what has traditionally been a spin-on market. The report also quantifies overall supplier shares as well as shares of specific photoresists and ancillary products. Photoresist supplier shares for all products in 2008 are illustrated below: Photoresist Supplier Share
Report Contents1. Executive Summary
2. Methodology
3. Forecast Drivers
4. Spin-on Technology Review
5. Vacuum Deposited Technology
6. Tools And Emerging Technologies
7. Market Assessment And Forecasts
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