Strategic Cost Model — Materials Edition

A Collaboration of Linx and IC Knowledge

Based on the ITRS, the Strategic Cost Model – Materials Edition projects costs, equipment and materials requirements to 2026 for various device categories.  The model details wafer costs, equipment set details and key consumables for a selected type of fab with a specific wafer start capacity in a given region.

The Strategic Cost Model – Materials Edition:

• Contains process blocks to build the devices and calculate mask steps
• Uses an extensive set of lithography calculations to understand the lithography schemes and added processing steps required, which also significantly drive costs
• Provides for flexibility on when both EUV and 450mm wafers enter production

1. Device Categories and Process Options:

ASIC

• Power options – HP, LOP, LSTP
• High-k gate oxide processes – Gate First or Gate Last
• Threshold voltages and number of gate oxides
• Transistor type options – Bulk Transistor, FDSOI, Multi Gate, Multi Gate III-V/Ge
• Embedded memory options – eDRAM, eFlash
• Number of metal layers

DRAM

• Access transistor options – RCAT, FinFET, VCT
• Peripheral date dielectric options – SiOn and High-k
• Capacitor structure options – Cylinder, Pedestal
• Capacitor materials options – top electrode, dielectric and bottom electrode.

FeRAM

• Capacitor structure options – Stack, 3D
• Capacitor materials options – top electrode, dielectric and bottom electrode.

MPU

• Gate oxide type – SiON, Gate First and Gate Last High-k
• Threshold voltage and number of gate oxide thicknesses
• Transistor type options – Bulk Transistor, FDSOI, Multi Gate, Multi Gate III-V/Ge
• Embedded memory options – eDRAM, eFlash
• Metal layers

MRAM

• Capacitor materials options – top electrode, dielectric and bottom electrode.

NAND 2D

• Cell type options – FG or CT

NAND 3D

• Number of 8 layer 3D stacks options

NOR CT, NOR FG, PCRAM, RF

• Multiple options

RRAM 2D

RRAM 3D

2. Wafer Cost Outputs

3. Equipment Counts & Outputs

4. High Level Consumables Output

Note:  This is a high level output.  Additional cost and equipment segmentation data is also provided.

5. Detailed Consumables Output

Materials Covered

• ALD — Device spacers, DRAM capacitors, Flash 3D, Flash CT, HKMG, PCM
• CMP — Slurries and pads for copper, barrier, DSL, HKMG, Oxide, Poly, STI, W
• CVD—  III V Channel, capping oxide, Spacers, Ply plugs, DRAM caps, DRAM Gate, High-K Gate
• ILD — Low-K, Logic Gate, ONO, Pad nitride, Passivation, PMD, STI, Strain, W, NF3, NH3, SiH4, WF6
• Litho — By Wavelength – Rinses, BARCs, Developer, HM, Resist, Pre Wet, Si Arc, SOC, TARC, Top coat
• Plating — Copper, CoWP
• PVD — Al, TaN, Ta, Cu, TaRu, IrO2, PZT, HKMG, TiN, Ni, W, NiCr
• Spin-on — Low-K, PMD, STI

Note: All materials can be adjusted for volume, value, dispense volumes, etc.

Completion

The model was completed in April 2012 and is updated multiple times per year.

Benefits

• Runs in Excel
• Updates on a regular basis
• Assist in understanding future devices now
• Companywide license